(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, in particular, to a method for reducing SAS resistance at a cell region of the semiconductor device.
(b) Description of the Related Art
Recently, as flash memories are widely utilized and price competition grows, various technologies have been developed for reducing the sizes of the devices. One of those is a self aligned source (SAS) technique.
The SAS technique is a method for reducing the cell size in a bit line direction and is essentially adopted for below −0.25 μm line width technology since it can reduce a gap between the gate and the source such that the cell size can be reduced about 20% with the introduction of the SAS technique.
However, the conventional SAS technique has a drawback in that the contact resistance of the source per cell dramatically increases because the SAS region is formed along the trench profile.
In the meantime, the below −0.25 μm or below −0.18 μm technology utilizes a shallow trench isolation (STI) technique for fabricating most semiconductor devices.
That is, the STI technique and the SAS technique are essential to reduce the cell size in a word line direction and a bit line direction, respectively. However, simultaneous adaptation of these two techniques causes a dramatic increase in the source resistance.
Especially, in the case of flash memory the reduction of the cell size may require increased depth of the trench due to a relatively high internal voltage, resulting in deterioration of the source resistance.
Conventional ion implantation techniques for the flash memories have been disclosed in the U.S. Pat. Nos. 6,524,914 and 6,448,608.
In case of As (arsenic) ion implantation for flash memory, the resistance per cell increases to be about 780 Ohm when the depth of the trench is 3600 Å, while the resistance per cell is about 400 Ohm when the trench depth is 2400 Å.
Also, in the case of P ion implantation, the resistance per cell increases to be about 450 Ohm with the trench depth of 3600 Å, while it is 250 Ohm with the trench depth of 2400 Å.
In case of an embedded flash, it is required that the reading and programming operation to be unaffected by the source resistance. However, since the trench depth of the logic transistor is 3500 Å in the flash memory cell adopted the 0.18 μm technology and the As ion implantation, the resistance per cell becomes 700–900 Ohm which is double of the required resistance, resulting in bad effects such as degradation of cell programming and reduction of reading speed.
In order to solve this problem, it can be considered to additionally implant the P (phosphorous) ions. FIG. 1 is a graph illustrating variation of the source resistance to the trench depth when only the As is ion implanted and the As and additional P are ion implanted, respectively. As shown in FIG. 1, the As and additional P implantation shows much reduction of the source resistance compared to the case of the As ion implantation.
Even though it is expected that the source resistance decreases by implanting the additional P ions after the gate formation, however, the channel length becomes shortened as much as about 0.24 μm, resulting in a punch through problem.
Also, the additional ion implantation has a shortcoming of hindering minimization of the proposed device.